Computer systems typically use inexpensive and high density dynamic random access memory (DRAM) chips for main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promulgated by the Joint Electron Devices Engineering Council (JEDEC). DDR DRAMs use conventional DRAM memory cell arrays with high-speed access circuits to achieve high transfer rates and to improve the utilization of the memory bus. For example, DDR4 DRAMs use memory cell arrays that require 12-15 nanosecond (ns) access times, but access large amounts of data and serialize the data at speeds up to 3.2 giga transfers per second (GT/sec) corresponding to a memory clock frequency of 1.6 gigahertz (GHz). The transfers use pseudo-open-drain techniques with on-die termination for good transmission line performance. While it is possible to operate a point-to-point interface at that rate to achieve fast transfers, it has become increasingly difficult for memory controllers to operate at fast enough speeds to schedule memory accesses.
A typical DDR memory controller maintains a queue to store pending read and write requests to allow the memory controller to pick the pending requests out of order and thereby to increase efficiency. For example, the memory controller can retrieve multiple memory access requests to the same row in a given rank of memory (referred to as “page hits”) from the queue out of order and issue them consecutively to the memory system to avoid the overhead of precharging the current row and activating another row repeatedly. However scanning and picking accesses from a deep queue while taking advantage of the bus bandwidth available with modern memory technologies such as DDR4 has become difficult to achieve with known memory controllers.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.